Backside and edge/bevel defects are among those that have silently crept up to the surface of the world of yield-limiting defects. The presence of contamination at the backside of a wafer can compromise up to 10% yield of today's advanced semiconductor devices at multiple process steps such as lithography, diffusion, cleans, CMP, and CVD film deposition. Backside defects are not limited to contamination and damage and they also include mechanical scratches that can lead to wafer breakages in the subsequent high-temperature processes. With 300 mm wafers, significantly more real estate is located at the wafer edge. Edge-yield losses, typically 10 to 40% when normalized and compared to center die yield, has therefore become a major concern.
The increased automation (less manual handling) and the advanced topography requirement of solely using DSP (double side polished) wafers for 300 mm manufacturing also have driven more significant challenges to recognize systematic issues early in the production line.